page 1 of 5 www.cd4power.com ADSD-1410S dual 14-bit, 10msps sampling a/d converter general description the ADSD-1410S is a functionally complete, dual 14-bit, 10msps, sampling a/d converter. its standard, 40-pin, triple-wide smt dip contains two fast-settling sample/hold amplifiers, two 14-bit a/d converters, multiplexed output buffers, a precision reference, and all the timing and control logic necessary to operate from either two or a single start convert pulse. the ADSD-1410S is optimized for wideband frequency- domain applications and is fully fft tested. the adsd- 1410s requires only 5v supplies and typically consumes 1.6 watts. the digital output power supply is capable of directly driving 5v or 3v logic systems. models are available in either commercial 0 to +70c or military -55 to +125c operating temperature ranges. input/output connections figure 1. ADSD-1410S functional block diagram features ? 14-bit resolution; 10msps sampling rate ? functionally complete; 2.5v input range ? no missing codes over full temperature range ? edge-triggered ? 5v supplies, 1.6 watts ? 76db snr, C83db thd ? ideal for both time and frequency domain applications " - 3 " " " " " " " " " " " " " " 4 ) - ) . ' ! . $ # / . 4 2 / , , / ' ) # / & & 3 % 4 ! $ * 5 3 4 ! ! . ! , / ' ) . 0 5 4 ! 2 ! . ' % n 3 ( 6 $ $ n 3 ( 2 % & " 5 & & % 2 " 5 & & % 2 / & & 3 % 4 ! $ * 5 3 4 " ! . ! , / ' ) . 0 5 4 " % . ! " , % ! % . ! " , % " 3 4 ! 2 4 # / . ! 3 4 ! 2 4 # / . " % / # " n 6 6 ! ! ' . $ $ ' . $ . # % / # ! ! $ # ! $ # 6 2 % & pin function pin function 1 input a 40 input b 2 +5va 39 +5va 3 analog ground 38 analog ground 4 n.c. 37 n.c. 5 offset a 36 offset b 6 range 35 n.c. 7 1.6v ref 34 eoc a 8 analog ground 33 analog ground 9 C5v 32 C5v 10 enable a 31 enable b 11 start a 30 start b 12 vdd 29 eoc b 13 bit 14 (lsb) 28 bit 1 (msb) 14 bit 13 27 bit 2 15 bit 12 26 bit 3 16 bit 11 25 bit 4 17 bit 10 24 bit 5 18 bit 9 23 bit 6 19 bit 8 22 bit 7 20 dgnd 21 dgnd
ADSD-1410S page 2 of 5 www.cd4power.com analog inputs min. typ. max. units input voltage range 2.5v volts input impedence 610 620 630 input capacitance 7 15 pf digital inputs logic levels logic "1" +2.4 volts logic "0" +0.8 volts logic loading "1" +10 a logic loading "0" C10 a performance integral non-linearity +25c (fin=10khz) 1 lsb 0 to +70c 1 lsb C55 to +125c 2 lsb differential non-linearity (f in = 10khz) +25c C0.99 0.5 +1.5 lsb 0 to +70c C0.99 0.5 +1.5 lsb C55 to +125c C0.99 0.75 +1.75 lsb offset error +25c (see figure 3) 0.25 0.5 %fsr 0 to +70c 0.25 0.5 %fsr C55 to +125c 0.5 0.8 %fsr gain error +25c (see figure 3) 0.3 0.6 %fsr 0 to +70c 0.3 0.6 %fsr C55 to +125c 0.6 0.8 %fsr no missing codes 14 bits C55 to +125c resolution 14 bits outputs output coding offset bin. logic level logic "1" v dd = +5v +3.8 volts v dd = +3.3v +2.48 volts logic "0" v dd = +5v +0.5 volts v dd = +3.3v +0.5 volts logic loading "1" v dd = +5v C8 ma v dd = +3.3v C4 ma logic loading "0" v dd = +5v +8 ma v dd = +3.3v +4 ma internal reference voltage, +25c +1.5 +1.6 +1.7 volts 0 to +70c +1.5 +1.6 +1.7 volts external current 5 ma dynamic performance min. typ. max. units total harm. distort. ( C0.5db) dc to 500khz C84 C80 db 500khz to 5mhz C83 C77 db signal-to-noise ratio (w/o distortion, C0.5db dc to 500khz 74 76 db 500khz to 5mhz 74 76 db signal-to-noise ratio (and distortion, C0.5db) dc to 500khz 72 75 db 500khz to 5mhz 72 75 db spurious free dyn. range ? dc to 500khz C87 C82 db 500khz to 5mhz C86 C80 db two-tone imd distortion (f in = 4.85mhz, fs = 10mhz, C0.5db) C80 db input bandwidth (C3db) small signal (C20db input) 14 mhz large signal (C0.5db input) 14 mhz aperture delay time 10 ns aperature uncertainty 5 ps s/h acq. time , (to 0.003%fsr) step input 25 ns feedthrough rejection (f in = 5mhz) 85 db noise 250 vrms timing specifications conversion rate 1 10 mhz start convert high 25 50 500 ns start convert low 25 50 500 ns start convert to eoc delay 2 6 10 ns eoc to data valid delay 0 7 12 ns output enable delay 1 6 13 ns output disable delay 1 6 13 ns power requirements power supply ranges C5v ee supply C5.25 C5.0 C4.75 volts +5v cc supply +4.75 +5.0 +5.25 volts v dd supply +3.0 +5.0 v cc volts power supply currents C5v ee supply C100 C89 ma +5v cc supply +230 +245 ma v dd supply +2.0 +5.0 ma power dissipation 1.6 1.7 watts power supply rejection 0.01 %fsr%v physical/environmental oper. temp. range, ambient ADSD-1410S 0 +70 c ADSD-1410S-ex C55 +125 c storage temperature range C65 +150 c package type 40-pin, smt tdip absolute maximum ratings parameters limits units +5v cc supply (pins 2, 39) 0 to +6 volts C5v ee supply (pins 9, 32) 0 to C6 volts v dd supply (pin 12) C0.3 to (v cc +0.3) volts digital inputs (pins 10, 11, 30, 31) C0.3 to (v dd +0.3) volts analog input (pins 1, 40) 7 volts lead temp. (10 seconds) +300 c footnote: ? same specification as in-band harmonics and peak harmonics. functional specifications (t a = +25c, v cc = +5v, v dd = +5v, v ee = C5v, 10msps sampling rate,vin = 2.5v and a minimum 7 minute warmup unless otherwise specified.)
ADSD-1410S page 3 of 5 www.cd4power.com technical notes 1. rated performance requires using good high-frequency cir- cuit board layout techniques. connect the digital and analog grounds to one point, the analog ground plane beneath the converter. due to the inductance and resis- tance of the power supply return paths, return the analog and digital ground separately to the power supplies. figure 2. ADSD-1410S timing diagram calibration procedure 1. connect the converter per figure 3. apply a pulse of 50 nanoseconds typical to start convert (pin 11) at a rate of 2mhz. this rate is chosen to reduce flicker if led's are used on the outputs for calibration purposes. 2. zero (offset) adjustments apply a precision voltage reference source between analog input a (pin 1) and signal ground (pin 3), then adjust the reference source output per table 2. adjust trimpot r1 until the code flickers equally between 10 0000 0000 0000 and 10 0000 0000 0001. 3. repeat above step for analog input b (pin 40). use trimpot r2 for the zero (offset) adjustment . table 3. output coding 11 1111 1111 1111 +2.499695 +fs C 1lsb 11 1000 0000 0000 +1.875000 +3/4fs 11 0000 0000 0000 +1.250000 +1/2fs 10 0000 0000 0000 0.000000 0 01 0000 0000 0000 C1.250000 C1/2fs 00 1000 0000 0000 C1.875000 C3/4fs 00 0000 0000 0001 C2.499695 Cfs+1lsb 00 0000 0000 0000 C2.500000 Cfs output coding 2.5v +0.000153v table 2. offset adjustment input offset adjust range +1/2 lsb 4. to confirm proper operation of the device, vary the precision reference voltage source to obtain the output coding listed in table 3. msb lsb input range 2.5v bipolar scale 3 4 ! 2 4 # / . 6 % 2 4 % . ! " , % ! % / # $ ! 4 ! ! o r " / 5 4 n 3 e c p e r d i v i s i o n n 3 e c % . ! " , % " $ ! 4 ! / 5 4 $ a t a .
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ADSD-1410S page 4 of 5 www.cd4power.com thermal requirements the ADSD-1410S sampling a/d converter is fully characterized and specified over the commercial operating temperature (ambient) range of 0 to +70c and military temperature range of C55 to +125c (ex suffix). all room-temperature (t a = +25c) production testing is performed without the use of heat sinks or forced-air cooling. thermal impedance figures for each device are listed in their respective specification tables. these devices do not normally require heat sinks, however, standard precautionary design and layout procedures should be used to ensure devices do not overheat. the ground and power planes beneath the package, as well as all pcb signal runs to and from the device, should be as heavy as possible to help conduct heat away from the package. electrically- insulating, thermally-conductive "pads" may be installed underneath the package. minimal air flow over the surface can greatly help reduce the package temperature. figure 3. ADSD-1410S connection diagram notes: ? outputs are enabled by either turning enable a (pin 10) or enable b (pin 31) low for respective analog inputs a or b. a high on both enable a and enable b results in disabling the output bus (high z). see timing diagram for details. ! $ 3 $
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ADSD-1410S page 5 of 5 c&d technologies (datel), inc. 11 cabot boulevard, mansfield, ma 02048-1151 tel: 508.339.3000, 800.233.2765 fax: 508.339.6356 www.cd4power.com e-mail: sales@cdtechno.com datel makes no representation that the use of its products in the circuits described herein, or the use of other technical info rmation contained herein, will not infringe upon existing or future patent rights. the descriptions contained herein do not imply the granting of licenses to make, use, or sell equipment constructed in accordance therewith. specifications are subj ect to change without notice. the datel logo is a registered datel, inc. trademark. c&d technologies (ncl), ltd. milton keynes, england tel: +44 (0) 1908.615232 e-mail: mk@cdtechno.com c&d technologies (datel) s.a.r.l. montigny le bretonneux, france tel: +33 (0) 1.34.60.01.01 e-mail: france@cdtechno.com c&d technologies (datel) gmbh mnchen, germany tel: +49 (0) 89.544334.0 e-mail: munich@cdtechno.com c&d technologies kk tokyo and osaka, japan tel: +81 3.3779.1031, 6.6354.2025 e-mail: tokyo@cdtechno.com, osaka@cdtechno.com c&d technologies (datel) china shanghai, peoples republic of china tel: +86.50273678 e-mail: shanghai@cdtechno.com iso 9001:2000 registered www.cd4power.com ds-0559a 06/06 model number operating temp. range ADSD-1410S 0 to +70c ADSD-1410S-ex C55 to +125c ordering information mechanical dimensions inches (mm) contact c&d technologies (datel) for high-reliability versions 2.10 0.262 0.06 1.09 0.100 typ. 0.025 typ. 1.900 0.10 opening in shell to prevent fluid entrapment 0.015 thick copper leads bottom of leads to be coplanar to 0.005
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